1. Field of the Invention
The invention relates in general to a circuit for accessing data from a memory device and, in particular, to a circuit for reading data from a memory device using a data strobe to transfer data.
2. Description of Prior Art
FIG. 1A shows a conventional memory interface between a double data rate (DDR) dynamic random access memory (DRAM) device and a physical layer PHY in a memory controller, wherein a clock signal CLK, command signals CMD and address bits ADD are one way signals from a physical layer PHY to the DRAM device, and DQ/DQS are bidirectional signals. For a write operation, the physical layer PHY sends a write command to the DRAM device and then sends write data and write data strobe DQ/DQS to the DRAM device; for a read operation the physical layer PHY sends a read command to the DRAM device and then the DRAM device sends read data and read data strobe DQ/DQS back to the physical layer PHY.
FIG. 1B shows a conventional memory interface circuit connecting to a DRAM in which the memory interface circuit sends a read command CMD and address bits ADD along with a clock signal CLK through the memory interface to the DRAM, which then sends back read data strobe and read data DQ/DQS back to the memory interface in the memory controller. The received read DQS, RD_DQS, is shifted 90 degree in PHY to obtain RD_QDS90 for capturing the incoming data DQ. The PHY_CLK is transmitted through a buffer to obtain a clock signal CLK which is actually received by the memory device; and a FIFO is needed in the read path of the memory interface for synchronization between the internal clock PHY_CLK and the RD_QDS90 since the read DQS/DQ from the DRAM has no phase relationship with PHY_CLK due to PCB trace, PKG, IO, and DRAM delays.
FIG. 1C shows a timing diagram for various signals in the memory interface for a read operation. The PHY_CLK is aligned with the DDR_CLK which is actually received by the DRAM. In FIG. 2, the frequency of the PHY_CLK is twice the frequency of the DDR_CLK and the rising edge of the PHY_CLK is aligned with edges of the DDR_CLK. Because the RD_QDS90 is not aligned with the PHY_CLK, a FIFO is needed for synchronization, which will introduce read latency.
Due to power saving and noise issues, IOs, such as transmitters TXs, receivers RXs, and related circuits are only turned on in the actual read/write operations. In order to control the transmitters TXs and receivers RXs, a gate training to position a gate signal for turning on and off the transmitters TXs and receivers RXs is necessary. FIG. 1D shows a timing diagram for various signals for a gate training sequence. As shown in FIG. 1D, the gate training is performed by sending a read command, and then a gate signal GATE will be delayed to match the time window when the read DQS is back. After the gate signal is positioned, the gate signal can turn on the receivers RXs so that the read strobe signal and read data can be received through the receivers RXs to obtain the received read data strobe RD_DQS and received read data RD_DQ and the RD_DQS is shifted by 90 degree to sample the received read data RD_DQ.
Conventionally, a phase lock loop/delay locked loop (PLL/DLL) can be used for synchronization between two clock domains. Typically a digital DLL uses chains of delay elements in delay lines to produce locked delays. For example, a quarter cycle delay may be used to delay the read strobe signal.
FIG. 2 is a flowchart illustrating a write training of a semiconductor memory device, as disclosed in US patent publication (US20120284470A1), to adjust the phase of a data clock in order to get the maximum data valid window for capturing write data.
Referring to FIG. 2, the training performed between the semiconductor memory device and the data processor includes operation S301 of loading a data pattern, operation S302 of transferring the data pattern, operation S303 of checking an arrival time of the data pattern, operations S304 and S305 of advancing or delaying phase of the data clock, operation S306 of determining if an interface corresponds to data input/output timing after adjusting the phase of the data clock with respect to the arrival time of the data pattern, and operation S307 of adjusting the interface (UI) when the interface (UI) does not correspond to the data input/output timing. The operation S301 of loading the data pattern and the operation S302 of transferring the data pattern are performed by the semiconductor memory device, and the other operations S303 to S307 are performed by the data processor. However, the above disclosure in US patent publication (US20120284470A1) is for a write operation inside a memory device, not for a read operation in a memory controller or a memory interface circuit.
Conventional way to read data from DDR DRAM devices is to adjust read data strobe timing in the read data path, which requires a FIFO for synchronization between the read data strobe and the internal clock. Therefore, what is needed is an efficient way to read data from a memory device without using the FIFO for the synchronization.